The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed. For example, conventional IC processing strives to minimize divot formation in isolation features used to isolate various devices, such as field-effect transistor devices, from one another. Divot formation is minimized to reduce junction leakage. Consequently, this confines device performance to a top surface channel, which confines device performance boosting as device technology nodes scale down. Fin-like field-effect transistors (FinFET) devices have provided an additional sidewall channel, however, FinFET device processing is complex and costly when compared to conventional planar device processing. Accordingly, although existing IC devices and methods have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.